Ngspice Releases Info
A word of caution: This page has not been updated! The actual release as of January 2013 is ngspice-25!
- Bug fixing: most of the bugs that affected rework-15 have been fixed, thus ngspice is more stable, especially the xspice extension, the subcircuit (X devices) handling and the numparam library.
- New features: netlist syntax has been expandend allowing for end-of-line comments. A ".global" card has beed added to define global nodes, i.e. nodes that are not expanded in subcircuits. It is possible to define TC for resistors on the instance line. The editline library can be used instead of readline (no more GPL license violation).
- Porting: ngspice now works (with xspice extension) on Windows using MINGW/MSYS.
- Xspice simulator (with codemodel dynamic loading support): a mixed signal simulator built upon spice3.
- Cider simulator: a mixed level simulator built upon spice3
- - Numparam library: a library that allows for parameter substitution at netlist level
- Improved models: Diode model includes periphery effects and high level of injection effects, BJT and BJT2 enhanced. BSIM3 now includes ACM. BSIM4 implementation corrected.
- New models: VBIC (3 Terminals, no excess phase and thermal network), HiSIM.
- Frontend leaks closed. Now frontend works as it should.
- Many new example file.
- Xgraph plotting program included.
The spice code contains an option to debug frontend code, now this is available in configure as "--enable-ftedebug".
Enhancements to the code comes from Alan's contribute code, a description of improvements follows (extracted form Alan's mail):
Output File Format Changes:
- Rawfile format changed to PSPICE Probe format (Usable with Demo version of Microsim's Probe). (NOTE: Do not rely on this, we may revert to the old format in the next release).
- Text mode .OP results even though "rawfile" written.
- Internal device nodes are not saved to "rawfile" (reduces file size). Optionally, these internal nodes can be replaced by device currents and saved.
DC Convergence Enhancements:
- "Source-Stepping" algorithm modified with a "Dynamic" step size. After each successful step, the node voltages are saved, the source-factor is increased by the step-factor, and the step-factor is increased (for the next step). If the step fails, i.e. the circuit does not converge, the source-factor is set to the value from the previous successful step, the previously stored node voltages are restored, the step-factor is reduced, the source factor is increased by this smaller step-factor, and convergence is attempted again.
- Same thing done for "Gmin-stepping" algorithm.
- "Gshunt" option added. This sets the "diagGmin" variable used in the gmin-stepping algorithm to a non-zero value for the final solution. (Normally this is set to zero for the final solution). This helps for circuits with floating nodes (and for some others too).
- The Gmin implementation across the substrate diodes of MOS1, MOS2, MOS3, MOS6 and BSIM3 devices, and across BJT base-emitter and base-collector diodes, was incorrect. Correcting this dramatically improved DC convergence. (I think this also affects BSIM1 and 2 but I haven't fixed them yet !)
- The gm, gmb and gds calculations in the MOS3 model were all wrong. The device equations were fixed, leading to much improved convergence.
- The Vcrit value used for diode voltage limiting was calculated without taking into account the device area (and in some cases without using the temperature corrected saturation current). This could cause floating point overflows, especially in device models designed to be scaled by a small area, e.g. 2u by 2u diodes (area=4e-12). This is now fixed for Diode, BJT, MOS1, MOS2, and MOS3 models.
- The diode voltage limiting was modified to add negative voltage limiting. Negative diode voltages are now limited to 3*Vdp-10, where Vdp is the voltage from the previous iteration. If Vdp is positive, then the voltage is limited to -10V. This prevents some more floating point overflows. (Actually, I'm still playing with the best values for this).
- The Spice3 "fix" for the MOS3 gds discontinuity between the linear and saturated regions only works if the VMAX parameter is non-zero. A "tweak" has been added for the VMAX=0 case.
Transient Convergence Enhancements:
- Temperature correction of various diode capacitances was implemented slightly incorrectly, leading to capacitance discontinuities in simulations at temperatures other than nominal. This affected the Diode and MOS3 models.
- A mistake in the implementation of the MOS3 source-bulk capacitance model resulted in a charge storage discontinuity. This has been fixed.
- The level 2 MOSFET model seems to calculate Von and Vth values for the threshold and subthreshold values respectively, but then uses Vbin to calculate the Vdsat voltage used to find the drain current. However, a jump statement uses Von to decide that the device is in the "cutoff" region, which means that when this jump allows the drain current to be calculated, Vdsat can already be well above zero. This leads to a discontinuity of drain current with respect to gate voltage. The code is now modified to use Vbin for the jump decision. It looks like the code should actually use Vth as the threshold voltage, but since PSPICE and HSPICE both follow the original Berkeley code, this was left alone.
New Model Parameters:
- A PSPICE/HSPICE-like "M" device parameter (i.e. M devices in parallel) was added to the MOS1,2,3 and BSIM3 mosfet models.
Input Read-in and Checking:
- Numbers beginning with a + sign got the input routine confused. Fixed now.
- Attempts to nodeset (or .IC) non-existent nodes are flagged with a warning.
- PWL statements on Voltage or Current sources are now checked for "non-increasing" time-points at the start of the simulation. Previously each time-point was checked as it was reached during the simulation, which could be very annoying if you made a mistake which caused the simulation to fail after hours of run-time.
- A check which was performed at the end of each sub-circuit expansion was moved to the top level. This check makes sure that all sub-circuits have been defined, but in its original position, it meant that if a sub-circuit included ANY .MODEL statements at all, then ALL the models called in that sub-circuit must also be defined within that sub-circuit. Now SPICE behaves as expected, i.e. a subcircuit may define its own models, but may also use models defined at any level above.
- MOS devices reported only half of the Meyer capacitances, and did not include overlap capacitances, when reporting to the .OP printout, or when storing device capacitances to the "rawfile".
- The ideal switch devices had no time-step control to stop their controlling voltages/currents overshooting the switching thresholds. The time-step control has been modified to use the last two time points to estimate if the next one will move the controlling voltage/current past a switching threshold. If this looks likely, then the time-step is reduced.
- The "rawfile" writing routines have been modified to print the "reference value" to the console during the simulation. This lets the user see exactly how far and how fast the simulation is proceeding.
- .OP printout tidied up a lot to make the printout clearer.
- Analysis order changed to fix a "feature" where, if you ask for a .OP and a .TRAN in the same simulation, the node voltages printed out correspond to the .OP, but the device data was from the last timepoint of the .TRAN
There are other minor bug fixes, and changes to reduce compiler warnings. There are probably some more significant fixes which I've forgotten :-)
I have prepared a source cleaning patch.
- patches don't get polluted with differences between automatically generated Makefile.am files. Usually these make up the biggest part of the patches. This allows me to read the patch on the mailing list instead of sifting through 90% redundant and irrelevant changes.
- the shell script autogen.sh automatically regenerates the required files if the user has automake, autoconf and libtool installed.
- this feature is only valuable to developers, not to end users.
Usage of this patch, once incorporated:
- BSIM3V3.1 model as level 49. This is the version modified by Serban Popescu which understands the M parameter and implements HDIF.
- BSIM3V3.2 model al Level 50. This is the standard Berkeley version.
- Now the resistor model can accepts two different values for DC and AC resistance.
- dynamically loading of some device code as an experimental feature for the future GPL simulator. Thanks to Arno Peters and Manu Rouat.
- Patched the following bug (thanks to Andrew Tuckey for having supplied the patch).
- Wsw (current controlled switch) in subckt, parsing bug.
- scale factor in arbitrary source.
- bug in noise analysis.
- save segmentation faults.