Re: [ng-spice] Support for SMP ??
On Wed, 31 Jan 2001, James Swonger wrote:
> Well, I'm sitting here watching the marching window crawl on 3
> jobsright now; circuit is a new PWM design, a few op amps, few
> comparators, maybe a thousand MOS in digital gates (ahdl modeled),
> oscillator, etc. About 2500 elements in netlist using ahdl, over
> 4000 if logic is netlisted as transistors.
>
> This is spectreS, Cadence. With basically 100% of an UltraSparc
> (50% of a two-processor machine), evaluation takes about 3 minutes
> but the jobs run for anywhere between 30 minutes and 12 hours.
> A lot of chop and a lot of linear operation, transient runs take
> a while. In fact, I routinely overrun Cadence's time counter
> (32767 seconds, then wrap to negative reported time).
>
Such small circuits! :-)
To comment on the speed, and ahdl, .... I recall some discussion at
a small conference last year... (IEEE/ACM International Workshop on
behavioral modeling and simulation) VHDL-AMS, AHDL, Verilog-AMS,
... simulations tend to be consistently much slower than Spice
simulations. Several researchers reported this. One report
(Visheashanth Kasulasrinivas and Harold Carter at University of
Cincinnati) has good detail on this, using their own simulator
(SEAMS). His benchmarks range from 34 to 306 times slower.
Based on this, I would guess that both ACS and NG-SPICE would be much
faster, but that is only a guess. A change in algorithms could
easily make some cases faster and others slower.
As I understand, SEAMS is built around Spice. A compiler generates
code, which is linked in. Several of the commercial simulators that
support these analog modeling langrages take this approach.
It seems to me that behavioral modeling should not be slower, yet all
that I know of are. With a speed 300 times slower, it needs more
help than the 3x best case you would get from parallel processing.
Some serious work on the algorithms is needed.
> Big transient runs with "Save all" (all port currents, all node
> voltages) are a good test of both memory manager and transient
> solution speed.
"Save all" is a big resource consumer. You could end up with a
situation where the save time and memory manager overhead could be so
big as to hide the actual solution time.
This reveals a possible optimization. Spice saves all the nodes by
default. It would run faster if it didn't. This is one reason ACS
does not save anything by default.
>
> Suppose you ran this big inverter string with a pulse source for,
> say, 100-1000 clock periods. What is the partitioning of the run
> time expended then? Also, put enough nodal capacitance in for the
> clock frequency that the transient solution never "settles" and
> the timestep never gets to uprange.
What is needed here is heuristics to exploit repetition, latency, and
multi-rate. I have been planning to do this (or have someone do it)
for years, but for financial reasons I have not been able to put
enough time in on it. ACS has some code for it but it is incomplete.
The ACS "common" is part of work to support repetition. The queues
are there to exploit lanency and multi-rate. It is not done, so
there is not much improvement yet. The more important difference
between ACS and Spice is that its architecture makes these things
easier to do.
I just found out about a commercial simulator that does exploit
repetition.
> ..... As it stands now, I have
> SPICE decks that contain too many idiomatic/unsupported model
> params to run on other engines. .........
The simulator companies love that. It locks you in. I would love to
reverse that. In ACS, the parser is simple enough that it is easy to
support multiple formats. There is a C++ class that gives it perl
like parsing and more. I can knock out parsers with much less
development effort using it. The free simulators need to support
what the commercial ones have, with their syntax, and more.
Remember, most of the commercial ones are derived from the Free ones.
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