Re: [ng-spice] Design Document Comments


To ng-spice@ieee.ing.uniroma1.it
From Kev <kev@v-ms.com>
Date Fri, 08 Oct 1999 09:44:55 +0100
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Organization V2000 Project [Mixed Signal Simulation]
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Paolo Nenzi wrote:
> 
> On Thu, 7 Oct 1999, Manu Rouat wrote:
> 
...
> > My feeling is that we should stick to a true analog simulator,
> > at least in the beginning.
> 
> Yes, I agree, we should realize a sort of "switching model with dealy" for
> digital components, a sort of second order model. This can be sufficient
> to start.

I agree with that too.

> I would like to hear Kev for this, I am not sure that it is what he would
> like to do.

When I worked at MetaSoftware on Verilog-A & Verilog-AMS, we built a
mixed mode simulator on top of HSpice (Fortran!) by combining it with
a digital simulator.

The approach taken with the language was to provide the minimum
support on either side of the analog/digital boundary, and to be able
to automatically detect boundaries and insert modules using the new
constructs to do the conversion.

The key features on the analog side is a the ability to create a piece-wise
linear waveform (PWL) through an API, and/or a 'filter' that limits the slew
rate for digital signals, also required is the 'cross' function that detects
analog levels (for conversion back to digital).

On the digital side we added 'driver access', which allows the HDL programmer
to create accurate digital->analog conversions (avoiding a lot of the 'X'
conversion problems of older approaches).

> When I think to a mixed mode simulator I am thinking at a tool that can
> reliably simulate spice described subcircuits with verilog or VHDL
> described ones. I know that there are may ways to to that but I am a
> newbie in the filed and my ideas are not completely clear.

An old discussion on the elements of Verilog-AMS exists at:

  http://www.dnai.com/~orpheus/lrm/

The OVI folk are reworking their site at the moment, and will probably
post the latest LRM soon.

Regards,
Kev.

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