Re: [ng-spice] Mixed signal simulation.
I sat through an Antrim presentation the other day, and they
claim that their engine is a unified simulator which handles
four different modes internal to itself - event-driven,
relaxation, analog behavioral and SPICE. No process-to-
process sync/RPC to slow it down, and each section of the
circuit is supposed to be (maybe with some hand-fiddling)
sent to and solved by its appropriate simulator engine.
Told me they were working on a Linux port, but that
HP and Sun standard OSs were where the professional
market is at. But I guess they're young & hungry enough
to eat small potatoes, too.
>From: Paolo Nenzi <pnenzi@ieee.ing.uniroma1.it>
>Reply-To: ng-spice@ieee.ing.uniroma1.it
>To: ng-spice@ieee.ing.uniroma1.it
>Subject: Re: [ng-spice] Mixed signal simulation.
>Date: Thu, 12 Aug 1999 19:10:39 +0200 (CEST)
>
>
>
>On Thu, 12 Aug 1999, Kev wrote:
>
> > Hi,
> >
> > You should have received an invite to the "Freeware Verilog Tools"
> > e-Group.
>Yes.
> >
> > The reason I sent you it is because it is possible to build a Verilog-A
> > simulator (LRM attached) on top of Spice 3 (Antrim -
>http://www.antrim.com
> > are doing this).
>I gave a look at antrim web site. I did not understood very well what they
>are doing. I am relatively new to the world of analog extension of Verilog
>and VHDL, so you should be patient ;-).
>
>It seems that they translate verilog-AMS into spice3, am I correct ?
>Doing this way we loose the faster speed of event based simulators, am I
>correct ?
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