Mixed signal simulation.


To ng-spice@ieee.ing.uniroma1.it
From Kev <kev@v-ms.com>
Date Thu, 12 Aug 1999 13:28:12 +0100
Delivered-To mailing list ng-spice@ieee.ing.uniroma1.it
Mailing-List contact ng-spice-help@ieee.ing.uniroma1.it; run by ezmlm
Organization V2000 Project [Mixed Signal Simulation]
Reply-To ng-spice@ieee.ing.uniroma1.it
Sender v2k@v-ms.com

Hi,

You should have received an invite to the "Freeware Verilog Tools"
e-Group.

The reason I sent you it is because it is possible to build a Verilog-A
simulator (LRM attached) on top of Spice 3 (Antrim - http://www.antrim.com
are doing this).

I used to work at MetaSoftware (HSpice), where we built a Verilog-A with a
Verilog parser, HSpice and a C-code generator - it didn't take long; we just
converted the Verilog into Spice net-list and dynamically loaded the process
models, extra component types were added to support 'branches' (as described
in the LRM).

My expertise is more on the digital, parallel-processing mixed-signal side
of things, so I'm happy to see someone is going to support Spice 3, and
would be interested in collaborating to build a Verilog-AMS simulator. I
can do the parser/elaborator & code-generator stuff, but am not familiar
with the mathematics of the solver.

Later,
Kev.

-- 
http://www.v-ms.com
mailto:admin@v-ms.com   Mixed Signal Simulation

vams1_4.pdf


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